This invention relates to an integrated circuit having a latch circuit with a selection function for selecting plural input signals by a control signal, and taking them in and holding statically.
There is the direction toward higher integration as one of the technical trends of integrated circuits today, and it is attempted, in this direction, to curtail the design rules and simplify the circuit configuration. In particular, the latter means is executed in various circuits.
For instance, when setting up static parallel registers in a logic integrated circuit, conventionally, ordinary D-type latches were used to cause the individual data inputs to correspond to individual parallel data inputs, and the individual data outputs to correspond to individual parallel data outputs, and an enable signal as for parallel registers was obtained by commonly connecting the individual enable signal inputs. However, as the number of bits of parallel processing increased, it was necessary to reduce the area of the D-type latches to be used. To satisfy this demand, the inverter used to generate an inverted enable signal in the D-type latch is removed, and an inverted enable signal is supplied from outside, thereby reducing the area of the D-type latch. What is added to the hardware due to the application of the inverted enable signal is, in the minimum case, only one inverter and one wire serving as the trunk line.
On the other hand, some of the general-purpose TTL-ICs contain a circuit to select and latch plural signals by combining a selector and latch. In this circuit, too, an attempt has been made to simplify in order to improve the degree of integration, but since the circuit configuration is originally simple, it seems difficult to further improve the degree of integration.